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cm6900 pfc/pwm c ombo w/ i nrush c urrent c ontrol & s eparated pfcovp 2003/04/23 preliminary rev. 1.2 champion microelectronic corporation page 1 general description features patent filed #5,565,761, #5,747,977, #5,742,151, #5,804,950, #5,798,635 inrush current control separated pfc ovp pin separated power vcca and analog vcca separated power ground and analog ground additional folded-back current limit for pwm section. 23v bi-cmos process vin ok guaranteed turn on pwm at 2.5v instead of 1.5v internally synchronized leading edge pfc and trailing edge pwm in one ic slew rate enhanced transconductance error amplifier for ultra-fast pfc response low start-up current (100a typ.) low operating current (3.0ma type.) low total harmonic distortion, high pf reduces ripple current in the storage capacitor between the pfc and pwm sections average current, continuous or discontinuous boost leading edge pfc vcca ovp comparator low power detect comparator pwm configurable for current mode or voltage mode operation current fed gain modulator for improved noise immunity brown-out control, over-voltage protection, uvlo, and soft start, and reference ok the cm6900 is a controller for power factor corrected, switched mode power suppliers. power factor correction (pfc) allows the use of smaller, lower cost bulk capacitors, reduces power line loading and stress on the switching fets, and results in a power supply that fully compiles with iec-1000-3-2 specifications. intended as a bicmos version of the industry-standard ml4824, cm6900 includes circuits for the implementation of leading edge, average current, ?boost? type power factor correction and a trailing edge, pulse width modulator (pwm). the cm6900 has additional features besides all the features of cm6800. additional features are inrush current control, separated pfc ovp pin, separated power vcca pin and analog vcca pin, and separated power ground pin and analog ground pin. gate-driver with 1a capabilities minimizes the need for external driver circuits. low power requirements improve efficiency and reduce component costs. an over-voltage comparator shuts down the pfc section in the event of a sudden decrease in load. the pfc section also includes peak current limiting and input voltage brownout protection. the pwm section can be operated in current or voltage mode, at up to 250khz, and includes an accurate 50% duty cycle limit to prevent transformer saturation. 24 hours technical support---websim champion provides customers an online circuit simulation tool called websim. you could simply logon our website at www.champion-micro.com for details.
cm6900 pfc/pwm c ombo w/ i nrush c urrent c ontrol & s eparated pfcovp 2003/04/23 preliminary rev. 1.2 champion microelectronic corporation page 2 applications pin configuration desktop pc power supply internet server power supply ipc power supply ups battery charger dc motor power supply monitor power supply telecom system power supply distributed power sop-20 (s20) / pdip-20 (p20) top view 1 2 3 4 5 6 7 8 20 19 18 17 16 15 14 13 ieao i ac i sense v rms inrushstopb ss v dc ramp1 veao v fb v fb2 v ref v cca v ddd pfcout pwmout v ssd agnd ramp2 dc i limit 9 10 11 12 pin description operating voltage pin no. symbol description min. typ. max. unit 1 ieao pfc transconductance current error amplifier output 0 4.25 v 2 i ac pfc gain control reference input 0 1 ma 3 i sense current sense input to the pfc current limit comparator -5 0.7 v 4 v rms input for pfc rms line voltage compensation 0 6 v 5 inrushsto pb inrush current control pin, it is low when inrush current is high or during the start-up condition and it is vcca when inrush condition has been removed. 0 vcca v 6 ss connection point for the pwm soft start capacitor 0 vref+0.7 v 7 v dc pwm voltage feedback input 0 vref+0.7 v 8 ramp 1 (rtct) oscillator timing node; timing set by rt ct 1.2 3.9 v 9 ramp 2 (pwm ramp) when in current mode, this pin functions as the current sense input; when in voltage mode, it is the pwm input from pfc output (feed forward ramp). 0 vref+0.7 v 10 dc i limit pwm current limit comparator input 0 1 v 11 agnd analog ground 12 v ssd digital ground 13 pwm out pwm driver output 0 vddd v 14 pfc out pfc driver output 0 vddd v
cm6900 pfc/pwm c ombo w/ i nrush c urrent c ontrol & s eparated pfcovp 2003/04/23 preliminary rev. 1.2 champion microelectronic corporation page 3 15 v ddd digital power vcca- 0.3 vcca vcca+0. 3 16 v cca analog power 10 15 20 v 17 v ref buffered output for the internal 7.5v reference 7.5 v 18 v fb2 pfc transconductance voltage error amplifier input 0 2.5 3 v 19 v fb pfc transconductance voltage error amplifier input 0 2.5 3 v 20 veao pfc transconductance voltage error amplifier output 0 6 v simplified block diagram 7 vdc 15 vddd pfc ovp + - . pwm duty -1v uvlo sw spst s r q q + - s r q + - sw spst 3.5k 10 dc ilimit ss cmp duty cycle limit 4 vrms cm6900(on:13v/off:10v) vfb 19.4v mppfc clk 3 isense gmi + - . 14 pfc out 6 ss vcca pwm cmp mppwm vcca 11 agnd 0.5v sw spst vref pfcout 350 pfc cmp 16 vcca + - vcc ovp 17 vref + - pfc ilimit 2.75v gain modulator 9 ramp2 1.5v inrush current 13 pwm out vin ok + - . 2.5v vcca 1 ieao 8 ramp1 2.45v gmv + - . 5 inrushstopb + - s r q q vssd 350 3.5k 1.0v + - pwmout + - dc ilimit 7.5v reference 20ua 20 veao vddd s r q q uvlo 12 vssd 19 vfb 2 iac sw spst + - low power detect mnpwm 18 vfb2 mnpfc -1.8v oscillator
cm6900 pfc/pwm c ombo w/ i nrush c urrent c ontrol & s eparated pfcovp 2003/04/23 preliminary rev. 1.2 champion microelectronic corporation page 4 ordering information part number temperature range package CM6900IP -40 to 125 20-pin pdip (p20) cm6900is -40 to 125 20-pin wide sop (s20) absolute maximum ratings absolute maximum ratings are those values beyond which the device could be permanently damaged. parameter min. max. units v cca and p vdd 23 v ieao 0 4.5 v i sense voltage -5 0.7 v pfc out gnd ? 0.3 vcca + 0.3 v pwmout gnd ? 0.3 vcca + 0.3 v inrushstopb gnd ? 0.3 vcca + 0.3 v voltage on any other pin gnd ? 0.3 vref + 0.3 v i ref 10 ma i ac input current 1 ma peak pfc out current, source or sink 1 a peak pwm out current, source or sink 1 a pfc out, pwm out energy per cycle 1.5 j junction temperature 150 storage temperature range -65 150 operating temperature range -40 125 lead temperature (soldering, 10 sec) 260 thermal resistance ( ja ) plastic dip plastic soic 80 105 /w /w electrical characteristics unless otherwise stated, these specifications apply vcca=+15v, r t = 52.3k ? , c t = 470pf, t a =operating temperature range (note 1) cm6900 symbol parameter test conditions min. typ. max. unit voltage error amplifier (g mv ) input voltage range 0 5 v transconductance v noninv = v inv , veao = 3.75v 30 65 90 mho feedback reference voltage 2.45 2.5 2.55 v input bias current note 2 -1.0 -0.5 a output high voltage 5.8 6.0 v output low voltage 0.1 0.4 v sink current v fb = 3v, veao = 6v -35 -20 a source current v fb = 1.5v, veao = 1.5v 30 40 a open loop gain 50 60 db power supply rejection ratio 11v < v cca < 16.5v 50 60 db
cm6900 pfc/pwm c ombo w/ i nrush c urrent c ontrol & s eparated pfcovp 2003/04/23 preliminary rev. 1.2 champion microelectronic corporation page 5 electrical characteristics (conti.) unless otherwise stated, these specifications apply vcca=+15v, r t = 52.3k ? , c t = 470pf, t a =operating temperature range (note 1) cm6900 symbol parameter test conditions min. typ. max. unit current error amplifier (g mi ) input voltage range -1.5 0.7 v transconductance v noninv = v inv , veao = 3.75v 50 100 150 mho input offset voltage -12 12 mv input bias current -1.0 -0.5 a output high voltage 4.0 4.25 v output low voltage 0.65 1.0 v sink current i sense = +0.5v, ieao = 4.0v -65 -35 a source current i sense = -0.5v, ieao = 1.5v 35 75 a open loop gain 60 70 db power supply rejection ratio 11v < v cca < 16.5v 60 75 db pfc ovp comparator threshold voltage 2.70 2.77 2.85 v hysteresis 230 290 mv low power detect comparator threshold voltage 0.4 0.5 0.6 v vcca ovp comparator threshold voltage 19 19.4 20 v hysteresis 1.40 1.5 1.65 v pfc i limit comparator threshold voltage -1.10 -1.00 -0.90 v (pfc i limit v th ? gain modulator output) 80 200 mv delay to output (note 4) overdrive voltage = -100mv 250 ns dc i limit comparator threshold voltage 0.95 1.0 1.05 v delay to output (note 4) overdrive voltage = 100mv 250 ns v in ok comparator threshold voltage 2.35 2.45 2.55 v hysteresis 0.8 1.0 1.2 v gain modulator i ac = 100a, v rms = v fb = 1v 0.59 0.81 i ac = 100a, v rms = 1.1v, v fb = 1v 1.47 2.03 i ac = 150a, v rms = 1.8v, v fb = 1v 0.66 0.92 gain (note 3) i ac = 300a, v rms = 3.3v, v fb = 1v 0.21 0.29 bandwidth i ac = 100a 10 mhz output voltage = 3.5k*(i sense -i offset ) i ac = 250a, v rms = 1.1v, v fb = 1v 0.70 0.80 0.90 v oscillator initial accuracy t a = 25 66 75.5 khz voltage stability 11v < v cca < 16.5v 1 % temperature stability 2 %
cm6900 pfc/pwm c ombo w/ i nrush c urrent c ontrol & s eparated pfcovp 2003/04/23 preliminary rev. 1.2 champion microelectronic corporation page 6 electrical characteristics (conti.) unless otherwise stated, these specifications apply vcca=+15v, r t = 52.3k ? , c t = 470pf, t a =operating temperature range (note 1) cm6900 symbol parameter test conditions min. typ. max. unit total variation line, temp 68 84 khz ramp valley to peak voltage 2.5 v pfc dead time (note 4) 500 700 ns ct discharge current v ramp2 = 0v, v ramp1 = 2.5v 6.5 10.5 ma reference output voltage t a = 25 , i(v ref ) = 1ma 7.4 7.5 7.6 v line regulation 11v < v cca < 16.5v 10 25 mv 0ma < i(v ref ) < 7ma; t a = 0 ~70 10 20 mv load regulation 0ma < i(v ref ) < 5ma; t a = -40 ~85 10 20 mv temperature stability 0.4 % total variation line, load, temp 7.35 7.65 v long term stability t j = 125 , 1000hrs 5 25 mv pfc minimum duty cycle v ieao > 4.0v 0 % maximum duty cycle v ieao < 1.2v 90 95 % i out = -20ma at room temp 15 ohm i out = -100ma at room temp 15 ohm output low rdson i out = 10ma, v cca = 9v at room temp 0.4 0.8 v i out = 20ma at room temp 15 20 ohm output high rdson i out = 100ma at room temp 15 20 ohm rise/fall time (note 4) c l = 1000pf 50 ns pwm duty cycle range 0-45 0-47 0-49.3 % i out = -20ma at room temp 15 ohm i out = -100ma at room temp 15 ohm output low rdson i out = 10ma, v cca = 9v 0.4 0.8 v i out = 20ma at room temp 15 20 ohm output high rdson i out = 100ma at room temp 15 20 ohm rise/fall time (note 4) c l = 1000pf 50 ns supply start-up current v cca = 12v, c l = 0 100 150 a operating current 14v, c l = 0 3.0 7.0 ma undervoltage lockout threshold cm6900 12.74 13 13.26 v undervoltage lockout hysteresis cm6900 2.85 3.0 3.15 v note 1: limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions. note 2: includes all bias currents to other circuits connected to the v fb pin. note 3: gain = k x 5.375v; k = (i sense ? i offset ) x [i ac (veao ? 0.625)] -1 ; veao max = 6v note 4: guaranteed by design, not 100% production test.
cm6900 pfc/pwm c ombo w/ i nrush c urrent c ontrol & s eparated pfcovp 2003/04/23 preliminary rev. 1.2 champion microelectronic corporation page 7 typical performance characteristic 57 64 71 78 85 92 99 106 113 120 127 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3 vfb (v) transconductance (umho) voltage error amplifier (g mv ) transconductance 0 20 40 60 80 100 120 140 160 180 200 220 -500 -400 -300 -200 -100 0 100 200 300 400 500 isense (mv) transconductance (umho) current error amplifier (g mi ) transconductance 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 00.511.522.533.544.55 vrms (v) variable gain block constant (k) gain modulator transfer characteristic (k) 1 - ac offset gainmod mv 0.625) - (6 x i i i k ? = 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 00.511.522.533.544.55 vrms (v) gain gain ac offset sense i i i gain ? =
cm6900 pfc/pwm c ombo w/ i nrush c urrent c ontrol & s eparated pfcovp 2003/04/23 preliminary rev. 1.2 champion microelectronic corporation page 8 functional description the cm6900 consists of an average current controlled, continuous boost power factor correction (pfc) front end and a synchronized pulse width modulator (pwm) back end. the pwm can be used in either current or voltage mode. in voltage mode, feedforward from the pfc output buss can be used to improve the pwm?s line regulation. in either mode, the pwm stage uses conventional trailing edge duty cycle modulation, while the pfc uses leading edge modulation. this patented leading/trailing edge modulation technique results in a higher usable pfc error amplifier bandwidth, and can significantly reduce the size of the pfc dc buss capacitor. the synchronized of the pwm with the pfc simplifies the pwm compensation due to the controlled ripple on the pfc output capacitor (the pwm input capacitor). the pwm section of the cm6900 runs at the same frequency as the pfc. in addition to power factor correction, a number of protection features have been built into the cm6900. these include soft-start, pfc overvoltage protection, peak current limiting, brownout protection, duty cycle limiting, and under-voltage lockout. power factor correction power factor correction makes a nonlinear load look like a resistive load to the ac line. for a resistor, the current drawn from the line is in phase with and proportional to the line voltage, so the power factor is unity (one). a common class of nonlinear load is the input of most power supplies, which use a bridge rectifier and capacitive input filter fed from the line. the peak-charging effect, which occurs on the input filter capacitor in these supplies, causes brief high-amplitude pulses of current to flow from the power line, rather than a sinusoidal current in phase with the line voltage. such supplies present a power factor to the line of less than one (i.e. they cause significant current harmonics of the power line frequency to appear at their input). if the input current drawn by such a supply (or any other nonlinear load) can be made to follow the input voltage in instantaneous amplitude, it will appear resistive to the ac line and a unity power factor will be achieved. to hold the input current draw of a device drawing power from the ac line in phase with and proportional to the input voltage, a way must be found to prevent that device from loading the line except in proportion to the instantaneous line voltage. the pfc section of the cm6900 uses a boost-mode dc-dc converter to accomplish this. the input to the converter is the full wave rectified ac line voltage. no bulk filtering is applied following the bridge rectifier, so the input voltage to the boost converter ranges (at twice line frequency) from zero volts to the peak value of the ac input and back to zero. by forcing the boost converter to meet two simultaneous conditions, it is possible to ensure that the current drawn from the power line is proportional to the input line voltage. one of these conditions is that the output voltage of the boost converter must be set higher than the peak value of the line voltage. a commonly used value is 385vdc, to allow for a high line of 270vac rms . the other condition is that the current drawn from the line at any given instant must be proportional to the line voltage. establishing a suitable voltage control loop for the converter, which in turn drives a current error amplifier and switching output driver satisfies the first of these requirements. the second requirement is met by using the rectified ac line voltage to modulate the output of the voltage control loop. such modulation causes the current error amplifier to command a power stage current that varies directly with the input voltage. in order to prevent ripple, which will necessarily appear at the output of boost circuit (typically about 10vac on a 385v dc level), from introducing distortion back through the voltage error amplifier, the bandwidth of the voltage loop is deliberately kept low. a final refinement is to adjust the overall gain of the pfc such to be proportional to 1/vin2, which linearizes the transfer function of the system as the ac input to voltage varies. since the boost converter topology in the cm6900 pfc is of the current-averaging type, no slope compensation is required. pfc section inrush current control this section is an additional function besides cm6800 functions. the inrushstopb pin is low during inrush current condition. it happens during start-up and high input current when isense is less than ?1.8v. gain modulator figure 1 shows a block diagram of the pfc section of the cm6900. the gain modulator is the heart of the pfc, as it is this circuit block which controls the response of the current loop to line voltage waveform and frequency, rms line voltage, and pfc output voltages. there are three inputs to the gain modulator. these are: 1. a current representing the instantaneous input voltage (amplitude and waveshape) to the pfc. the rectified ac input sine wave is converted to a proportional current via a resistor and is then fed into the gain modulator at i ac . sampling current in this way minimizes ground noise, as is required in high power switching power conversion environments. the gain modulator responds linearly to this current. 2. a voltage proportional to the long-term rms ac line voltage, derived from the rectified line voltage after scaling and filtering. this signal is presented to the gain modulator at vrms. the gain modulator?s output is inversely proportional to v rms 2 (except at unusually low values of v rms where special gain contouring takes over, to limit power dissipation of the circuit components under heavy brownout conditions). the relationship between v rms and gain is called k, and is illustrated in the typical performance characteristics. 3. the output of the voltage error amplifier, veao. the gain modulator responds linearly to variations in this voltage.
cm6900 pfc/pwm c ombo w/ i nrush c urrent c ontrol & s eparated pfcovp 2003/04/23 preliminary rev. 1.2 champion microelectronic corporation page 9 the output of the gain modulator is a current signal, in the form of a full wave rectified sinusoid at twice the line frequency. this current is applied to the virtual-ground (negative) input of the current error amplifier. in this way the gain modulator forms the reference for the current error loop, and ultimately controls the instantaneous current draw of the pfc form the power line. the general for of the output of the gain modulator is: i gainmod = 2 rms ac v veao i x 1v (1) more exactly, the output current of the gain modulator is given by: i gainmod = k x (veao ? 0.625v) x i ac where k is in units of v -1 note that the output current of the gain modulator is limited around 228.47a and the maximum output voltage of the gain modulator is limited to 228.47ua x 3.5k=0.8v. this 0.8v also will determine the maximum input power. however, i gainmod cannot be measured directly from i sense . i sense = i gainmod -i offset and i offset can only be measured when veao is less than 0.5v and i gainmod is 0a. typical i offset is around 60ua. selecting r ac for iac pin iac pin is the input of the gain modulator. iac also is a current mirror input and it requires current input. by selecting a proper resistor r ac , it will provide a good sine wave current derived from the line voltage and it also helps program the maximum input power and minimum input line voltage. r ac =vin peak x 7.9k. for example, if the minimum line voltage is 80vac, the r ac =80 x 1.414 x 7.9k=894kohm. current error amplifier, ieao the current error amplifier?s output controls the pfc duty cycle to keep the average current through the boost inductor a linear function of the line voltage. at the inverting input to the current error amplifier, the output current of the gain modulator is summed with a current which results from a negative voltage being impressed upon the i sense pin. the negative voltage on i sense represents the sum of all currents flowing in the pfc circuit, and is typically derived from a current sense resistor in series with the negative terminal of the input bridge rectifier. in higher power applications, two current transformers are sometimes used, one to monitor the if of the boost diode. as stated above, the inverting input of the current error amplifier is a virtual ground. given this fact, and the arrangement of the duty cycle modulator polarities internal to the pfc, an increase in positive current from the gain modulator will cause the output stage to increase its duty cycle until the voltage on i sense is adequately negative to cancel this increased current. similarly, if the gain modulator?s output decreases, the output duty cycle will decrease, to achieve a less negative voltage on the i sense pin. cycle-by-cycle current limiter and selecting r s the i sense pin, as well as being a part of the current feedback loop, is a direct input to the cycle-by-cycle current limiter for the pfc section. should the input voltage at this pin ever be more negative than ?1v, the output of the pfc will be disabled until the protection flip-flop is reset by the clock pulse at the start of the next pfc power cycle. r s is the sensing resistor of the pfc boost converter. during the steady state, line input current x r s = i gainmod x 3.5k. since the maximum output voltage of the gain modulator is i gainmod max x 3.5k= 0.8v during the steady state, r s x line input current will be limited below 0.8v as well. therefore, to choose r s , we use the following equation: r s =0.7v x vinpeak/(2x line input power) for example, if the minimum input voltage is 80vac, and the maximum input rms power is 200watt, r s = (0.7v x 80v x 1.414)/(2 x 200) = 0.197 ohm. separated pfc overvoltage protection in the cm6900, pfc ovp is using vfb2, which is separated from vfb to sense ovp condition. the pfc ovp comparator serves to protect the power circuit from being subjected to excessive voltages if the load should suddenly change. a resistor divider from the high voltage dc output of the pfc is fed to vfb. when the voltage on vfb2 exceeds 2.75v, the pfc output driver is shut down. the pwm section will continue to operate. the ovp comparator has 250mv of hysteresis, and the pfc will not restart until the voltage at vfb drops below 2.50v. the vfb power components and the cm6900 are within their safe operating voltages, but not so low as to interfere with the boost voltage regulation loop. also, vcca ovp can be served as a redundant pfcovp protection. vcca ovp threshold is 19.4v with 1.5v hysteresis.
cm6900 pfc/pwm c ombo w/ i nrush c urrent c ontrol & s eparated pfcovp 2003/04/23 preliminary rev. 1.2 champion microelectronic corporation page 10 figure 1. pfc section block diagram error amplifier compensation the pwm loading of the pfc can be modeled as a negative resistor; an increase in input voltage to the pwm causes a decrease in the input current. this response dictates the proper compensation of the two transconductance error amplifiers. figure 2 shows the types of compensation networks most commonly used for the voltage and current error amplifiers, along with their respective return points. the current loop compensation is returned to v ref to produce a soft-start characteristic on the pfc: as the reference voltage comes up from zero volts, it creates a differentiated voltage on i eao which prevents the pfc from immediately demanding a full duty cycle on its boost converter. pfc voltage loop: there are two major concerns when compensating the voltage loop error amplifier, v eao ; stability and transient response. optimizing interaction between transient response and stability requires that the error amplifier?s open-loop crossover frequency should be 1/2 that of the line frequency, or 23hz for a 47hz line (lowest anticipated international power frequency). the gain vs. input voltage of the cm6900?s voltage error amplifier, v eao has a specially shaped non-linearity such that under steady-state operating conditions the transconductance of the error amplifier is at a local minimum. rapid perturbation in line or load conditions will cause the input to the voltage error amplifier (v fb ) to deviate from its 2.5v (nominal) value. if this happens, the transconductance of the voltage error amplifier will increase significantly, as shown in the typical performance characteristics. this raises the gain-bandwidth product of the voltage loop, resulting in a much more rapid voltage loop response to such perturbations than would occur with a conventional linear gain characteristics. the voltage loop gain (s) cv v dc eao 2 outdc in fb eao out fb eao out z * gm * c * s * v * v v 5 . 2 * p v v * v v * v v ? ? ? ? ? ? ? = z cv : compensation net work for the voltage loop gm v : transconductance of veao p in : average pfc input power v outdc : pfc boost output voltage; typical designed value is 380v. c dc : pfc boost output capacitor pfc current loop: the current amplifier, i eao compensation is similar to that of the voltage error amplifier, v eao with exception of the choice of crossover frequency. the crossover frequency of the current amplifier should be at least 10 times that of the voltage amplifier, to prevent interaction with the voltage loop. it should also be limited to less than 1/6th that of the switching frequency, e.g. 16.7khz for a 100khz switching frequency. the current loop gain (s) ci i s outdc sense eao eao off off isense z * gm * v 5 . 2 * l * s r * v i i * i d * d v ? ? ? ? ? ? =
cm6900 pfc/pwm c ombo w/ i nrush c urrent c ontrol & s eparated pfcovp 2003/04/23 preliminary rev. 1.2 champion microelectronic corporation page 11 z ci : compensation net work for the current loop gm i : transconductance of ieao v outdc : pfc boost output voltage; typical designed value is 380v and we use the worst condition to calculate the z ci r s : the sensing resistor of the boost converter 2.5v: the amplitude of the pfc leading modulation ramp l: the boost inductor there is a modest degree of gain contouring applied to the transfer characteristic of the current error amplifier, to increase its speed of response to current-loop perturbations. however, the boost inductor will usually be the dominant factor in overall current loop response. therefore, this contouring is significantly less marked than that of the voltage error amplifier. this is illustrated in the typical performance characteristics. i sense filter, the rc filter between r s and i sense : there are 2 purposes to add a filter at i sense pin: 1.) protection: during start up or inrush current conditions, it will have a large voltage cross rs which is the sensing resistor of the pfc boost converter. it requires the i sense filter to attenuate the energy. 2.) to reduce l, the boost inductor: the i sense filter also can reduce the boost inductor value since the i sense filter behaves like an integrator before going i sense which is the input of the current error amplifier, ieao. the i sense filter is a rc filter. the resistor value of the i sense filter is between 100 ohm and 50 ohm because i offset x the resistor can generate an offset voltage of ieao. by selecting r filter equal to 50 ohm will keep the offset of the ieao less than 5mv. usually, we design the pole of i sense filter at fpfc/6, one sixth of the pfc switching frequency. therefore, the boost inductor can be reduced 6 times without disturbing the stability. therefore, the capacitor of the i sense filter, c filter , will be around 283nf.
cm6900 pfc/pwm c ombo w/ i nrush c urrent c ontrol & s eparated pfcovp 2003/04/23 preliminary rev. 1.2 champion microelectronic corporation page 12 oscillator (ramp1) the oscillator frequency is determined by the values of r t and c t , which determine the ramp and off-time of the oscillator output clock: f osc = deadtime ramp t t 1 + the dead time of the oscillator is derived from the following equation: t ramp = c t x r t x in 3.75 v 1.25 v ref ref ? ? at v ref = 7.5v: t ramp = c t x r t x 0.51 the dead time of the oscillator may be determined using: t deadtime = 5.5ma 2.5v x c t = 450 x c t the dead time is so small (t ramp >> t deadtime ) that the operating frequency can typically be approximately by: f osc = ramp t 1 example: for the application circuit shown in the datasheet, with the oscillator running at: f osc = 100khz = ramp t 1 solving for c t x r t yields 1.96 x 10 -5 . selecting standard components values, c t = 390pf, and r t = 51.1k ? the dead time of the oscillator adds to the maximum pwm duty cycle (it is an input to the duty cycle limiter). with zero oscillator dead time, the maximum pwm duty cycle is typically 45%. in many applications, care should be taken that c t not be made so large as to extend the maximum duty cycle beyond 50%. this can be accomplished by using a stable 390pf capacitor for c t . pwm section pulse width modulator the pwm section of the cm6900 is straightforward, but there are several points which should be noted. foremost among these is its inherent synchronization to the pfc section of the device, from which it also derives its basic timing. the pwm is capable of current-mode or voltage-mode operation. in current-mode applications, the pwm ramp (ramp2) is usually derived directly from a current sensing resistor or current transformer in the primary of the output stage, and is thereby representative of the current flowing in the converter?s output stage. dci limit , which provides cycle-by-cycle current limiting, is typically connected to ramp2 in such applications. for voltage-mode, operation or certain specialized applications, ramp2 can be connected to a separate rc timing network to generate a voltage ramp against which v dc will be compared. under these conditions, the use of voltage feedforward from the pfc buss can assist in line regulation accuracy and response. as in current mode operation, the dc i limit input is used for output stage overcurrent protection. no voltage error amplifier is included in the pwm stage of the cm6900, as this function is generally performed on the output side of the pwm?s isolation boundary. to facilitate the design of optocoupler feedback circuitry, an offset has been built into the pwm?s ramp2 input which allows v dc to command a zero percent duty cycle for input voltages below 1.25v. pwm current limit the dc i limit pin is a direct input to the cycle-by-cycle current limiter for the pwm section. should the input voltage at this pin ever exceed 1v, the output flip-flop is reset by the clock pulse at the start of the next pwm power cycle. beside, the cycle-by-cycle current, when the dc ilimit triggered the cycle-by-cycle current, it also softly discharge the voltage of soft start capacitor. it will limit pwm duty cycle mode. therefore, the power dissipation will be reduced during the dead short condition. v in ok comparator the v in ok comparator monitors the dc output of the pfc and inhibits the pwm if this voltage on v fb is less than its nominal 2.45v. once this voltage reaches 2.45v, which corresponds to the pfc output capacitor being charged to its rated boost voltage, the soft-start begins. pwm control (ramp2) when the pwm section is used in current mode, ramp2 is generally used as the sampling point for a voltage representing the current un the primary of the pwm?s output transformer, derived either by a current sensing resistor or a current transformer. in voltage mode, it is the input for a ramp voltage generated by a second set of timing components (r ramp2 , c ramp2 ),that will have a minimum value of zero volts and should have a peak value of approximately 5v. in voltage mode operation, feedforward from the pfc output buss is an excellent way to derive the timing ramp for the pwm stage. soft start start-up of the pwm is controlled by the selection of the external capacitor at ss. a current source of 20a supplies the charging current for the capacitor, and start-up of the pwm begins at 1.25v. start-up delay can be programmed by the following equation: c ss = t delay x 1.25v a 20
cm6900 pfc/pwm c ombo w/ i nrush c urrent c ontrol & s eparated pfcovp 2003/04/23 preliminary rev. 1.2 champion microelectronic corporation page 13 where c ss is the required soft start capacitance, and the t dealy is the desired start-up delay. it is important that the time constant of the pwm soft-start allow the pfc time to generate sufficient output power for the pwm section. the pwm start-up delay should be at least 5ms. solving for the minimum value of c ss : c ss = 5ms x 1.25v a 20 + ? r bias = 9ma 5ma 15v 18v + ? choose r bias = 214 ? the cm6900 should be locally bypassed with a 1.0f ceramic capacitor. in most applications, an electrolytic capacitor of between 47f and 220f is also required across the part, both for filtering and as part of the start-up bootstrap circuitry.
cm6900 pfc/pwm c ombo w/ i nrush c urrent c ontrol & s eparated pfcovp 2003/04/23 preliminary rev. 1.2 champion microelectronic corporation page 14 leading/trailing modulation conventional pulse width modulation (pwm) techniques employ trailing edge modulation in which the switch will turn on right after the trailing edge of the system clock. the error amplifier output is then compared with the modulating ramp up. the effective duty cycle of the trailing edge modulation is determined during the on time of the switch. figure 4 shows a typical trailing edge control scheme. in case of leading edge modulation, the switch is turned off right at the leading edge of the system clock. when the modulating ramp reaches the level of the error amplifier output voltage, the switch will be turned on. the effective duty-cycle of the leading edge modulation is determined during off time of the switch. figure 5 shows a leading edge control scheme. one of the advantages of this control technique is that it required only one system clock. switch 1(sw1) turns off and switch 2 (sw2) turns on at the same instant to minimize the momentary ?no-load? period, thus lowering ripple voltage generated by the switching action. with such synchronized switching, the ripple voltage of the first stage is reduced. calculation and evaluation have shown that the 120hz component of the pfc?s output ripple voltage can be reduced by as much as 30% using this method.
cm6900 pfc/pwm c ombo w/ i nrush c urrent c ontrol & s eparated pfcovp 2003/04/23 preliminary rev. 1.2 champion microelectronic corporation page 15 application circuit (current mode) d4 r21 c31 r28 r2b ramp2 r26 d8 c3 d9 t2a r1b r25 c24 q1 r2a vin ac t1b r27 c16 d5 d3 r5a c21 r22 c9 d12 r20a +382v ref r5d c11 r9 c2 c20 c19 c14 d14 vdc +12v return r32 vcc r11 d6 u6 cm6900/01/24 2 1 3 13 14 15 16 4 5 6 7 8 9 10 11 12 17 18 19 20 iac ieao i-sense pwm-out pfc-out vdd vcc vrms inr ss vdc ramp1 ramp2 ilimit agnd vss vref vfb2 vfb veao r18 c25 c6 r5e r31b r24 r5c c23 c12 r7a d13 r5b t2b r30 +12v r12 d7 r19 d11b r3 r6 q3 r20b d2 r23 l2 u3 t2c c13 c17 c22 c1 r17 inrush r13 c25 r4 +12 v out r31a q5 tp1 c7 d10 t1a r15 c8 c30 r7b c4 d11a c33 c10 q4 r31 c32 r8 l1 c18 r10 -+ u2 r16 r14 d1 c5 q2 r1a c15 inrush
cm6900 pfc/pwm c ombo w/ i nrush c urrent c ontrol & s eparated pfcovp 2003/04/23 preliminary rev. 1.2 champion microelectronic corporation page 16 application circuit (voltage mode) r31 d7 1n4002 l1 pwm_in r2 r61 470 c49 r14 ss pwm_dc iload r16a r11 10n q12 emc filter c23 c56 iso1 r34 4.7 pwm_vout pwm_rload 500m ilimit r57 r48 ic10 c34 r5 c33 pfc_vout inrush vcc r1 r24 22 ivin vdc r64 r17a q3 iac c41 c7 isense ivin_emc r35 4.7 r66 100 c55a l3 d6 1n4002 q7 q2n2904 pfc_dc pfc_vout 100n vref vfb c46 r28 22 veao r18 r60 ibias r26 18k ieao r22 22 c47 d12 1n4148 r46 vref 10n c17 r59 c44 t1 t 2:3 vcc pfc_vin c53 c43 c54 c30 c8 c45 r44 r15 vfb2 pfc_out 10n ic18 d5 c4 r16a l4 pfc_vout vcc c22 c3 c19 d5 r62 c57 10n l2 ic17 c50 d8 mur1100 100n ilimit ilimit ivin d9a c31 q6 q2n2222 cm6900/01/24 2 1 3 13 14 15 16 4 5 6 7 8 9 10 11 12 17 18 19 20 iac ieao i-sense pwm-out pfc-out vdd vcc vrms inr ss vdc ramp1 ramp2 ilimit agnd vss vref vfb2 vfb veao r58 zd1 6.8v iboot l5 vrms c40 c2 c51 c15 r65a rt1 r32a c52 10n c10 q2 vin ac r27 100k u1 cm431 r10 r33 q1 q2n2222 c14 vref r65a pwm_out c38 r49 c55a q1 d9b r45 470p r25 10k c48 inrush c39 r3 r23 75 r6 il4 100n vcc r29 10k r43 d13 mur1100 q2 q2n2904 pfc_vin d4 c18 c22 vdc r12 r17a d10 mur1100 r13 r32 il1 inrush r63 1u vcc d16 1n4148 r56
cm6900 pfc/pwm c ombo w/ i nrush c urrent c ontrol & s eparated pfcovp 2003/04/23 preliminary rev. 1.2 champion microelectronic corporation page 17 package dimension 20-pin pdip (p20) pin 1 id 20-pin sop (p20), 0.300? wide pin 1 id
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